A central processing unit (CPU) includes a plurality of execution units or schedulers. Such schedulers include an address generation unit (AGU), a floating point (FP) unit, a load (LD) unit, a store (ST) unit, and an integer (INT) unit. Each scheduler, after executing the scheduler's operation, writes the scheduler's results in a physical register file (PRF).
In computer architecture, register renaming eliminates false data dependencies arising from reuse of architectural registers by successive instructions that do not have any real data dependencies between them. The elimination of such false data dependencies reveals more instruction-level parallelism in the instruction stream. Excessive write ports on the PRF are required to support parallel write from any scheduler. In an out-of-order system, this creates multiple writers on the PRF. To improve instructions per cycle (IPC), the PRF is growing and more write ports are added at the cost of power consumption.
For example, with 8 schedulers and 256 physical register file entries with a width of 64, for each entry, it is required to decode out of the 8 write ports, which write port to write to that entry (i.e., select between 8 data to write in each location). Thus, a total of 8 write ports and 256 8-1 multiplexer (MUX) for a width of 64 each may be required.
Machine language programs specify reads and writes to a limited set of registers specified by the instruction set architecture (ISA). These are the architectural registers. Programs written for a given instruction set will specify operations that read and write those architectural registers. In standard renaming schemes, the machine converts the architectural registers referenced in the instruction stream into physical registers. These physical registers are then used by the execution units to perform the instruction.